1. Field of the Invention
The present invention generally relates to a microcomputer and a debugging method and, particularly, to a microcomputer and a debugging method that check the operation as rewriting memory contents.
2. Description of Related Art
A flash memory is more highly impact-resistant compared with a hard disk and therefore suitable for use as a storage device of a microcomputer that is integrated in a vehicle or the like which is subject to external impacts. Recent flash memories have large capacity and are thus capable of storing a large amount of program and data.
In the operational check of the microcomputer having a flash memory which does not include a circuit for storing program or data, the operation is checked after writing program or data into the flash memory by using a dedicated recording device such as a flash writer.
In the implementation of debugging on such a microcomputer, it is inefficient to remove the flash memory from the microcomputer, rewrite the flash memory by using a flash writer, and incorporate the flash memory back to the microcomputer each time modifying the program or data. Further, the repetitive rewriting on the flash memory causes the degradation of durability of the flash memory.
In order to save the labor of replacing the flash memory upon debugging, a technique of incorporating a memory called Temporary RAM (which is abbreviated herein to the “TRAM”) for use in the debugging is proposed in Japanese Unexamined Patent Application Publication No. 11-110244, for example. According to this technique, the program or data to be rewritten is written to the TRAM. If the rewriting of program or data is needed during the debugging, a debug circuit rewrites the program or data not in the flash memory but in the TRAM. Then, CPU reads the modified program or data not from the flash memory but from the TRAM. This enables the debugging without replacing the flash memory.
In this configuration, however, the CPU and the TRAM are connected by only one bus. Further, the debug circuit for rewriting the TRAM does not have a function to check the status of the bus. It is thus necessary to prevent simultaneous access from the CPU and the debug circuit to the TRAM.
Therefore, in the debugging method of the related art, the debug circuit transmits a break signal to the CPU and thereby forcibly stops the operation of the CPU prior to rewrite on the TRAM so as to make sure that the CPU does not access the TRAM.
In this method, however, it is necessary to stop the CPU each time rewriting program or data, which causes low operating efficiency. Further, since the CPU is stopped, it is unable to perform the operational check in accordance with the actual operation.
As described in the foregoing, the present invention has recognized that the debugging method of the related art has low operating efficiency and is incapable of performing the operational check in accordance with the actual operation due to the requirement for stopping the CPU each time rewriting program or data.